module Handshake_Protocol #(DATA_WIDTH = 8)(
  input                   clk,
  input                   rst_n,

  input                   valid_i, //from pre-stage
  input [DATA_WIDTH-1:0]  data_i,  //from pre-stage
  input                   ready_i, //from post-stage

  output                  ready_o, //to pre-stage
  output                  valid_o, //to post-stage
  output [DATA_WIDTH-1:0] data_o   //to post-stage
);

reg                  valid_o_r;
reg [DATA_WIDTH-1:0] data_o_r;

always @(posedge clk)begin
  if(~rst_n)
    valid_o_r <= 1'b0;
  else if(valid_i)
    valid_o_r <= 1'b1;
  else if(~valid_i)
    valid_o_r <= 1'b0;
end

always @(posedge clk)begin
  if(~rst_n)
    data_o_r <= {DATA_WIDTH{1'b0}};
  else if(valid_i)
    data_o_r <= data_i;
end

assign ready_o = ready_i;
assign valid_o = valid_o_r;
assign data_o  = data_o_r;

endmodule
